Magnetic random access memory (MRAM) that incorporates a MTJ as a magnetic memory storage cell (MMC) is a strong candidate to provide a high density and non-volatile storage solution for future memory applications. An MRAM array is generally comprised of an array of parallel first conductive lines on a horizontal plane, an array of parallel second conductive lines on a second horizontal plane spaced above and formed in a direction perpendicular to the first conductive lines, and an MTJ formed at each location where a second conductive line crosses over a first conductive line. A first conductive line may be a word line while a second conductive line is a bit line or vice versa. Each MTJ has a tunnel barrier layer sandwiched between two ferromagnetic layers. One is a pinned layer whose magnetization direction is fixed and the other ferromagnetic layer is a free layer whose magnetization direction can rotate under the influence of an externally applied magnetic field that is generated by applying a current in each of the adjacent first and second conductive lines. Alternatively, the magnetization direction of the free layer is switched by applying a different level of current through the MMC as in a spin-torque or STT-RAM device.
A MRAM chip includes a plurality of MMCs which are integrated with a CMOS (complementary metal oxide semiconductor) circuit. In a MMC, data information is stored in two different magnetic states represented by a “0” where the magnetization directions of the pinned and free layers are in a parallel alignment and a “1” where the magnetization directions of the pinned and free layers are in an anti-parallel alignment. The two magnetic states have a different resistance for tunneling current across the tunnel barrier that is a thin dielectric material. During a write operation, a magnetic state for one or more MMCs is changed from a “0” to a “1” or vice versa. In a read operation, the stored information in the MMC is read by sensing the magnetic state of the junction through a sensing current flowing through the junction in a current perpendicular to plane (CPP) or in a current in-plane (CIP) fashion.
Referring to FIG. 1a, a simplified version of a MMC is depicted wherein a word line 10 is aligned in an x-axis direction and an overlying bit line 18 is aligned in a y-axis direction. There is a dielectric layer 11 separating the word line 10 from a bottom electrode 12 to isolate the two electrical components from each other. A magnetic tunnel junction is enclosed in a dielectric layer 13 and comprises a lower magnet 14 including a pinned layer and typically an anti-ferromagnetic (AFM) layer (not shown), a tunnel barrier layer 15, an upper magnet or free layer 16, and a top electrode 17. The lower magnet is electrically connected through the bottom electrode and a via (not shown) to a CMOS transistor while the upper magnet 16 contacts the top electrode 17 and is electrically connected to the bit line (BL) 18.
One of the challenges associated with MRAM fabrication is to control the distance between the free layer in a MTJ and an overlying conductive line such as BL 18 since the distance plays an important factor in determining the efficiency of switching the magnetization direction in the free layer during a write process. A conventional MRAM fabrication involves defining the MTJ layers by patterning a mask layer on the top surface of top electrode 17 and then using an etch process to transfer the pattern through the MTJ stack of layers. Once the MTJ cell is defined, the mask is stripped and the dielectric layer 13 is deposited to a thickness that covers all of the MTJ layers. Then a chemical mechanical polish (CMP) method is employed to planarize the top surface so that dielectric layer 13 is coplanar with top electrode 17. In a well controlled CMP process, there are no protrusions of top electrode 17 above the top surface of dielectric layer 13, and the dielectric layer which is usually an oxide has a smooth surface with no dishing or bumps at the MTJ interface. Thereafter, a BL 18 is formed within a second dielectric layer 19 and contacts the top electrode 17. A second CMP process is generally used to make BL 18 coplanar with second dielectric layer 19. Although this method is straightforward and can be successfully implemented for a MMC with a thick top electrode having a thickness greater than 200 Angstroms, there are several practical issues encountered for fabricating a MMC with a thin top electrode 17 (<200 Angstroms thick) for advanced MRAM devices as illustrated in FIGS. 1b-1f. 
To maximize the magnetic influence of a bit line on a free layer in a MTJ, one option is to make the bit line as close as possible to the MTJ tunnel barrier and free layer. One way to accomplish this effect is to employ a relatively thick TE but position the bottom of the bit line substantially below the top surface of the top electrode as shown in FIG. 1b. This design can easily lead to degradation in MTJ performance since the top electrode 17 is usually made of Ta and has a higher resistance than Cu in BL 18. The intrusion of top electrode 17 into BL 18 will decrease the electrical conductivity through the bit line. Furthermore, since the shape of BL 18 is no longer linear due to the intrusion by top electrode 17, the local magnetic field generated by BL 18 is reduced thus making the writing operation to free layer 16 more difficult. It is also difficult to control the amount of intrusion of top electrode into BL 18 and in some cases, the bit line may contact the free layer 16 to further deteriorate magnetic performance.
Another way to maximize the magnetic influence of BL 18 on free layer 16 is to use a very thin top electrode 17 as in FIG. 1c. Because of film thickness non-uniformity, etch rate non-uniformity and morphologic variations across the surface of BL interlevel dielectric layer (ILD) 19, a certain amount of overetch should be applied to form an opening in which BL 18 is deposited. However, it is difficult to adjust the amount of overetch because one does not want to etch substantially beyond the top surface of top electrode 17 and risk forming a situation as described with regard to FIG. 1b. On the other hand, the etch must proceed to an extent that the top surface of all top electrodes 17 are uncovered so that BL 18 can make contact with each MTJ in the MRAM array. A slight etching process drift can easily cause an open circuit between top electrode 17 and BE 18 for some MMC cells if the initial over etching margin is not set correctly. As a result of under etching, a gap with thickness d of BL ILD 19 is formed between top electrode 17 and BL 18 to cause an open circuit.
Another concern related to plasma etching of BL ILD 19 is the tendency to create a ditch or sub-trench along the boundary of BL ILD and top electrode 17 as illustrated in FIG. 1d. The sub-trench may extend deep into dielectric layer 13 and actually contact the sidewalls 14s of the lower magnet 14. After BL 18 is deposited, the sub-trench is filled with a bit line portion 18t and can short the MTJ barrier 15 by forming an electrical circuit around the tunnel barrier such that the BL 18 directly contacts lower magnet 14. This undesirable condition may occur for a thin top electrode even for a setting where there is a right amount of overetch to ensure that all BL ILD 19 is removed from the top surface of top electrode 17.
Referring to FIG. 1e, the sub-trench 18t problem may become worse if the MTJ cell has a small size and/or more tapered sidewalls 14s. Then, even for a thick top electrode 17, the plasma etch process to form an opening (not shown) in BL ILD 19 has a strong tendency to create a deep sub-trench that contacts sidewalls 14s. 
In a worst case scenario shown in FIG. 1f, all factors mentioned previously including a thin top electrode 17, small size MTJ, more tapered sidewalls 14s, and long over etch combine to produce a large filled sub-trench 18t that shorts the MTJ.
Considering all of the potential fabrication issues referred to in FIGS. 1b-1f, there is a need to improve the MRAM fabrication sequence and thereby improve production yields and enhance magnetic performance.
In U.S. Pat. No. 6,174,737, a method of forming a MRAM structure is disclosed where a top electrode in the form of a conductive line runs over a plurality of magnetic memory cells. A dielectric layer is deposited on the conductive line and then a trench which is aligned orthogonal to the conductive line is formed within the dielectric layer. The trench is filled with a lower conductive layer and an upper bit line. Overetching into the dielectric layer surrounding the magnetic memory cells is prevented by forming an etch stop layer that is coplanar with the conductive line. However, this method teaches the formation of a top electrode separately from the magnetic memory cell which is generally not practiced in current designs where higher efficiency is achieved by forming the top electrode simultaneously with the magnetic memory cell.
U.S. Pat. No. 7,045,368 describes a MRAM fabrication method where the MTJ ILD layer is planarized in two steps. A CMP process removes an upper portion of the dielectric film above the capping layer and a RIE process further thins the MTJ ILD layer to 50 to 190 Angstroms below the top surface of the MTJ. This method does not prevent shorting or sub-trenches from forming especially when the capping layer (top electrode) is less than 200 Angstroms thick.
In U.S. Patent Application Publication 2009/0078927, a composite hard mask is employed to define a MTJ shape. However, the invention does not provide a means to control subsequent etching processes from forming a sub-trench along the MTJ.
U.S. Pat. No. 6,969,895 describes a controlled method of forming a bit line by using a sacrificial layer on the capping layer in the MTJ. The sacrificial layer is removed after the MTJ is defined and affords a consistent capping layer thickness but does not have any controlled influence on a later BL ILD etch step than can cause sub-trenches.
In U.S. Patent Application Publication 2007/0023806, a relatively thick hard mask is formed between a MTJ and a bit line. Although the additional thickness of the hard mask prevents bit line ILD etching from reaching the MTJ, it does add extra distance between MTJ and bit line and can therefore degrade free layer switching capability.